The occurrence of high voltage spikes, namely electrostatic discharge (ESD), induced by uncontrollable charge imbalance between a chip's input or output pads and externally grounded or pre-charged objects, affects the reliability and functionality of semiconductor integrated circuits (ICs), commonly resulting in hard-failure for advanced technologies. Various protection techniques have been developed to protect circuitry from ESD. Prior techniques have attempted to implement protection to the circuits by using one or more devices to provide current paths between the IC's pins and one or both circuit voltage supplies to shunt the current of unpredictable and destructive signals. Such ESD protection is required to be transparent during the normal operation of the circuit, so that the ESD protection does not negatively impact the performance of the remaining IC circuitry. A major problem, however, is that current devices for advanced silicided CMOS/BiCMOS technologies for high level of ESD protection purpose are unavailable. Further, standard devices, optimized for performance not for power, are ineffective in handling the high power obtained during an ESD event.
The shrinking of device dimensions in advanced technologies, aimed at both high performance and high density circuits, often results in ICs that are more sensitive to ESD events. This consequence of the driving technology downscaling is mainly associated with different tradeoffs that improve performance by decreasing the power handling capability. The reduction of core circuit and ESD protection area involving shallow junctions, low junction breakdown voltage, thin gate oxide, low bias operating voltage, high circuit density, mixed-voltage interface environments, packaging constraints, and rigid layout design rules, is discussed by Voldman, “A review of latchup and electrostatic discharge (ESD) in BiCMOS silicon germanium technologies: Part I ESD”, Microelectronics Reliability, pp. 323-340, 2005.
To provide the necessary ESD protection, standard devices for on-chip ESD protection can occupy a considerable area of the IC, as discussed in the article by Amerasekera et al., “The impact of technology scaling on ESD robustness and protection circuit design”, IEEE Transaction on Components, Packaging, and Manufacturing Technology-Part A, pp. 314-320, 1995 Moreover, increasing the size of the traditional protection structures to levels comparable with the core circuit dimensions does not guarantee that the ESD protection requirements are reached. This condition can degrade the ESD performance in sub-micron mixed-signal ICs and diminish the potential advantages of the technology downscaling.
ESD protection devices designed to undergo in high conductivity modulation upon activation, overcome the limitations of standard ESD protection structures. These kinds of devices can be realized by properly combining opposite doping concentration types, P (free holes are majority) and N (free electrons are majority), in (P-N)-(P-N) double injection lateral structures, namely thyristor or SCR (silicon controlled rectifier) type devices.
FIG. 1A shows a cross sectional view of the SCR in the prior art. The anode 24 and cathode 22 terminals are typically connected to the pad to be protected and one of the power rails. The (P−N)−(P−N) structure is obtained by the layers 12, 14, 18, and 20. FIG. 1B shows a circuital schematic representation of the device shown in FIG. 1A. The schematic shows the SCR consisting of two coupled BJTs, pnp 26 and npn 28, and two resistors, one associated with the N-well 30 and the second associated with the P-type substrate 32, corresponding to the electrodes 16 and 10, respectively. This device maintains the high-impedance off-state while the anode-cathode voltage is higher than the reference voltage in the cathode but lower than the so called trigger voltage, which is the voltage where the device reaches the on-state condition. For anode-cathode voltage below zero, conduction is obtained at a forward biased junction. The SCR device was originally built in custom technologies and studied in the prior art for high power electronics purposes, as discussed, for example in the article by Temple, “MOS Controlled Thyristors—A New Class of Power Devices,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1609-1618, 1986.
Some approaches have attempted to design thyristor-type devices to provide ESD protection. The use of SCRs as input protection for early processes is shown in U.S. Pat. Nos. 4,400,711; 4,484,244; 4,567,500; and 4,595,941. In these patents, SCR-type structures were designed using the given process for protection from the PAD to VSS (reference voltage power rail) and from the PAD to VDD (high voltage power rail). Disclosed are devices that allow a unidirectional current path from one of the power rails to the pad, or that create a coupled BJT transistor structure able to conduct high current when the voltage transients exceed the predetermined values (either negative or positive) from the pad to the power rails. These devices are aimed at clamping the input voltage within the range of the power supply, for instance in circuits for signal processing in early TVs.
A scheme of Schottky barrier diodes address the protection for IC applications which are required to interface with outside circuits operating at higher voltage. In these cases, a diode is connected between the input terminal and the power supply line for blocking voltages from the input terminal which are greater than the power supply voltage. These schemes are designed for an integrated circuit (IC) fabricated using geometries about 0.5 micrometers where the input and bidirectional input/output (I/O) circuits have to withstand an input voltage which can exceed the IC supply voltage. For example, the IC may operate at 3.3 volts, but must have the ability to interface with other circuits having 5 volt logic swings. This ability is commonly called “5 volt friendly.” This alternative ESD solution is directed to a very close interface voltage and does not provide a solution for a circuit that should operate at voltage range exceeding three or more times the power supply.
Other schemes proposed the use of SCR structures to provide higher conducting voltage. In these schemes, the trigger and holding voltage are increased by using stacked devices. This solution also involves stringent design of the triggering circuit and normally requires the addition of external triggering circuit components. Moreover, they can be very sensitive to the technology design rules.
Previous art also considers PN junctions stacked in series. In such cases, the protection structure starts conducting at voltages below/above the operating voltage. If the appropriated area is used, the diode structure provides a medium level of ESD protection at voltages lower/higher than the conducting voltage defined by the stacked diodes operating in combine reverse breakdown or Zener condition, and forward conduction. There are several known disadvantages of this system, however. For example, parallel/series clamping diodes require a large area, are slow-response, exhibit undesirable parasitic capacitance and leakage current, and have undesirably high “on” resistance. Also, such large diode clamps require a low impedance return path. Without a low impedance return path, the effectiveness of these large diode clamps is greatly reduced. Additionally, large clamping devices are not standard devices and are not practiced in advanced high density integrated circuits.
Wang et al., “On a dual-polarity on-chip electrostatic discharge protection structure,” IEEE Transaction on Electron Devices, pp. 978-984, 2001, and U.S. Pat. No. 6,365,924 B1, propose a structure built in a p-type substrate for dual polarity symmetric operating voltages exceeding the power supply. In this structure, variations in the P-base and N-well profiles defined by the process highly affect the trigger voltage that can be obtained. As such, it is limited to only a few processes that provide this flexibility. The electrodes of Wang et al. define two symmetric interconnections, a first to the pad and a second to the reference power rail, which is normally ground. Wang et al. discuss the characteristics of the device in the specific process, and performance and extension of the protection devices are restricted to the specified case of discussion. By symmetry in this device, the main region for injection of minority carriers is the same region for the current path in both polarities. This increases the risk of hot spot generation and non-uniform current distribution when dimensions in the device are increased for higher levels of ESD protection which poses scaling problems. A further limitation of the device is its inability to provide asymmetric dual polarity characteristics and non-uniform operating condition in a parallel device array.
Isolation of the protection devices from the rest of the circuit should also be addressed for dual-polarity protection devices. Customized guard-rings are fundamental components for isolating devices in the circuit, and are important for isolating ESD protection devices that are required to sustain high voltage/high current conditions. Guard ring structures, however, have traditionally constrained the minimum and maximum conducting voltages (below VSS and above VDD power rails) that can be obtained in the devices. U.S. patent application Ser. No. 11/032,154 filed Jan. 11, 2005, and U.S. Provisional Application Ser. No. 60/643,692 filed Jan. 12, 2005, also discuss ESD devices and are incorporated herein by reference in their entirety.
Thus, there is a need to overcome these and other problems of the prior art associated with conventional ESD devices. Further, there is a need for an ESD protection structure that includes isolation from the core circuit and that can provide the ESD protection in emerging, advanced technologies, thereby allowing for migration of semiconductor products that require interface with external circuits that operate at much higher or lower symmetric/asymmetric voltages, or even including high level of ESD immunity requirements.